Power semiconductor modules comprise, as a rule, at least one power semiconductor chip sited on a substrate and which because of the heat dissipated in its operation needs to be cooled. For this purpose, the substrate is press-bonded to a heatsink. Disposed between the substrate and the heatsink is a thermal compound, e.g., a thermal paste for optimum thermal conductance to the heatsink. To avoid air inclusions the thermal compound evens out irregularities in the substrate and heatsink if there is a sufficient amount of the thermal compound. On the other hand, the thermal conductance—assuming there is no problem with air inclusions—is all the more effective the thinner the coating of the thermal compound.
Shown in FIG. 1 is a cross-section through a portion of a conventional power semiconductor module 100 pressed against a heatsink 200. The power semiconductor module 100 comprises a substrate 2 with a ceramic core 20 topped and bottomed by a top-side metallization 21 and bottom-side metallization 22 respectively. A power semiconductor chip 1 is soldered by means of a solder layer 15 to the top-side metallization 21. The contact pressure force F for pressing the substrate 2 against the heatsink 200 is achieved by a stamp 25 pressing on the substrate 2 alongside the power semiconductor chip 1.
In such an assembly the substrate 2 is deformed by the contact pressure force F so that the smallest spacing between the substrate 2 and the heatsink 200 does not materialize in the portion beneath the power semiconductor chip 1 but alongside the latter. The drawback in this arrangement is that the thermal conductance between the substrate 2 and heatsink 200 is an optimum not ideally beneath the power semiconductor chip 1 but alongside the latter.
Although it is basically possible to apply the pressure top-down on the semiconductor chip, as could be achieved with a stamp, for example, such a stamp, to properly distribute the force would have to have a certain minimum cross-sectional area on the chip to prevent the latter from being damaged. But, because of the high currents needed to flow through the power semiconductor chip 1 as a rule, it is advantageous that the chip 1 is connected with as low an impedance as possible. This is achievable by circuiting a plurality of leads in parallel, for example in the form of bond wires, each bonded to a metallization topping the chip practically completely. However, an expansive stamp has a large footprint on the metallization topping the chip making it no longer available for fabricating the bonds.
Although a contact of adequate low impedance is also achievable with one or a few thick bond wires, the redundancy is then lacking should a bond malfunction, for instance. When one or more leads malfunction the operating temperature rises in the remaining functioning bond wires which, in turn is detrimental to managing the temperature of the module.